Silicon dioxide, SiO.sub.2, is commonly used as a dielectric material in semiconductor manufacturing. The dielectric may be formed by various methods, such as by plasma deposition, TEOS decomposition and thermal growth. Regardless of the manner of oxide formation, it is necessary to remove or pattern the oxide. One way to pattern oxide is by plasma etching, also known as dry etching, as described in Plasma Etching, by Manos and Flamm, copyright 1989, pages 159-165. Another way to pattern oxide is by wet etching as described in Semiconductor Integrated Circuit Processing Technology, by Runyan and Bean, copyright 1990, pages 264-266. Hydrofluoric acid (HF) mixed with water and often buffered with ammonium fluoride is a standard silicon dioxide wet etchant. Typically, the semiconductor wafer is immersed into a tank containing the wet etchant and thereafter removed where it may be dipped into other tanks for rinsing or cleaning the wet etchant from the wafer.
A problem with wet etching silicon dioxide and subsequent tank rinsing is particle generation. Particles are small minute bits or pieces of silicon dioxide that remain on the surface of the semiconductor wafer after rinsing. Sometimes, the particles do not necessarily cause problems. However, as linewidths continue to shrink, small particles that may not have affected larger linewidth devices, become more problematical as they do affect smaller linewidth devices. As an example, dynamic random access memories (DRAMs) of the 16 megabit variety are typically manufactured with around 0.5 micron design rules. 64 megabit DRAMs are typically manufactured with around 0.35 micron design rules. 256 megabit DRAMs will be manufactured with around 0.25 micron linewidths and 1 gigabit DRAMs will have even smaller linewidths. See Semiconductor Memories, by Prince, copyright 1991, page 114.
Particle control is a problem regardless of the type of memory cell architecture used for the DRAM. Two commonly used types of memory cell architectures are trench type and stack type. These are described in Semiconductor Memories, by Prince, copyright 1991, pages 138-141. Another relatively new type of memory cell architecture is the crown. Crown type memory cells are described in the following papers:
1. Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAM's, by Kaga et al., IEEE Transactions On Electron Devices, Vol. 38 No. 2, February 1991, pages 255-261; and PA1 2. Fabrication Process for Container and Crown Electrodes in Memory Devices, by Kotecki et al., IBM Technical Disclosure Bulletin, Vol. 38 No. 11, November 1995. PA1 1. U.S. Pat. No. 5,612,241, issued Mar. 18, 1997 to Arima and assigned to Mitsubishi; PA1 2. U.S. Pat. No. 5,545,582, issued Aug. 13, 1996 to Roh and assigned to Samsung; PA1 3. U.S. Pat. No. 5,491,103, issued Feb. 13, 1996 to Ahn et al. and assigned to Samsung; PA1 4. U.S. Pat. No. 5,354,705, issued Oct. 11, 1994 to Mathews et al. and assigned to Micron; PA1 5. U.S. Pat. No. 5,278,091, issued Jan. 11, 1994 to Fazan et al. and assigned to Micron; PA1 6. U.S. Pat. No. 5,270,241, issued Dec. 14, 1993 to Dennison et al. and assigned to Micron; PA1 7. U.S. Pat. No. 5,238,862, issued Aug. 24, 1993 to Blalock et al. and assigned to Micron; and PA1 8. U.S. Pat. No. 5,162,248m issued Nov. 10, 1992 to Dennison et al. and assigned to Micron.
Crown type memory cells are discussed in the following U.S. patents:
Prior art FIGS. 1a-f show a sequence of manufacturing steps used to make a crown type memory cell. Prior art FIGS. 1a-f correspond respectively to FIGS. 7a-f of the Kaga et al. IEEE article described in publication 1 above. The following manufacturing description also comes from the Kaga et al. article. To be noted is that a HF solution is used to remove SiO.sub.2 in conjunction with FIGS. 1e and 1f.
Prior art FIG. 1a shows a semiconductor substrate 10 having word lines 12 covered by a SiO.sub.2 layer 14. After removal of the thin SiO.sub.2 layer 14 at the data line contact region 16, polycyrstalline Si 18, WSi.sub.2 20 and SiO.sub.2 22 are deposited on the surface of the wafer using a chemical vapor deposition (CVD) technique as illustrated in prior art FIG. 1b.
In the step of prior art FIG. 1b, the polycrystalline Si surface 18 is planarized using an etch-back method to make a planar WSi.sub.2 surface 20.
Next, the data lines are formed by anisotropic dry etching. Then a sidewall SiO.sub.2 region 24 is formed using CVD and an anisotropic dry etching method as illustrated in prior art FIG. 1c. During this step, capacitor contacts are automatically formed on the Si surface. Then, selective polycrystalline Si layers 26 are formed on the contacts.
In FIG. 1d, a Si.sub.3 N.sub.4 layer 28 and a SiO.sub.2 layer 30 are deposited using CVD. The Si.sub.3 N.sub.4 layer 28 (about 200 nm) fills both the word-line spaces and data-line spaces. Because these spaces are approximately 0.3 .mu.m, almost a flat Si.sub.3 N.sub.4 surface can be created.
After SiO.sub.2 /Si.sub.3 N.sub.4 layer deposition, the SiO.sub.2 /Si.sub.3 N.sub.4 layer is etched using anisotropic dry etching. Then a 100 nm thick n-type polycrystalline Si layer 32 is deposited using a phosphorus doped CVD technique as illustrated in FIG. 1e.
After filling the holes with SiO.sub.2 by using CVD and an etch-back method, the polycrystalline Si layer 32 is anisotropically etched. Then the filled SiO.sub.2 and the SiO.sub.2 layer 30 on the Si.sub.3 N.sub.4 layer 28 are removed using a HF solution. Next, a crown-shaped polycrystalline Si electrode is formed. Then, a Ta.sub.2 O.sub.5 film 34 is deposited using CVD. In this step, a two-step oxygen-ambient annealing method is applied to reduce current leakage and to improve film reliability. Finally, a tungsten film 36 is sputtered as illustrated in FIG. 1f.
Kaga et al. is silent as to how the SiO.sub.2 layer 30 is removed using a HF solution. Possibly, the wafer was dipped into a solution of HF followed by dipping the wafer into a rinse as described above. However, such technique could possibly generate thousands of particles which could settle back onto the wafer surface. It is also possible that the wafer was put into a vapor HF chamber to remove the oxide.
FSI Corporation of Chaska, Minn., United States of America manufactures an anhydrous vapor HF etcher called the "Excaliber ISR-200". U.S. Pat. No. 4,749,440, issued on Jun. 7, 1988 to Blackwood et al. and assigned to both FSI and Texas Instruments describes an apparatus and process for anhydrous vapor HF processing. Among the advantages provided over wet etching, are uniform, repeatable and controllable etching and smooth surfaces. However, even the advantageous techniques described in the patent may not be enough to successfully minimize particle disruption for ULSI devices such as DRAMS having complex topographies. What is needed is a new technique for advanced wafer oxide cleaning which greatly minimizes particles.
It is accordingly an object of the invention to provide a new method for etching oxide from semiconductor wafer surfaces which minimizes particle defects.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having the benefit of the following specification.